Principal Engineer ASIC Physical Design - Vancouver, BC

Job Description Summary

Our client is seeking a Principal ASIC Physical Design Engineer to join their highly-skilled ASIC development team. The ideal candidate is deeply experienced in the design of complex SoCs using RTL to GDS flows. Working closely with other members of the ASIC design team and silicon implementation partners to create industry-leading edge computing solutions. The candidate should be self-motivated and focused, comfortable collaborating with geographically dispersed teams, passionate about all aspects of ASIC development, driven by team success, and eager to make a difference in a start-up environment.

 Job Responsibilities

• Guidance and oversight of technical aspects of ASIC provider physical design and DFT activities including top-level floor plan

• Synthesis and constraints development for top-level and block-level, including both internally developed and third-party IP

• Ownership of power intent including UPF development, power island/clock gating strategies, and power analysis

• Timing and physical verification of ASIC provider deliverables, logical equivalency checking

• ECO implementation and verification

• Development of physical design tool flows inside Perceive

 Required Skills

·         MSc or BSc in Electrical Engineering, Computer Engineering, Computer Science, or related field with at least 10 years of experience with RTL to GDS physical design

·         Hands-on experience of the entire SoC/ASIC design flow including synthesis, floorplanning, CTS, P&R, timing closure, DRC/LVS checks, power analysis, EM & IR analysis using industry standard tools & methodologies

·         Solid experience with physical synthesis, block and full-chip implementation with current industry P&R/STA flows and tools

·         Experience with power intent development (UPF), multi-voltage, power islanding & power intent verification

·         Experience with clock tree synthesis (CTS) of multi-clock designs

·         Experience with static timing analysis (STA) and formal equivalency checks

·         Experience with top and block level floor plan development, implementing power grid and area/congestion optimization

·         Ability to work effectively with both internal and external teams

·         Strong coding skills in Verilog, Tcl, Python and shell scripting

·         Excellent written and verbal communication skills

 Preferred Skills

·         Experience with 14/16nm or smaller process nodes is strongly preferred

·         Sign-off experience with reliability, signal integrity, noise, power, physical and DFM

 Our client offers highly competitive compensation and an opportunity to work in an innovative environment that will change the semiconductor environment.

 Contact: Amanda Du Toit amanda@corporate.bc.ca